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Writing Testbenches. Functional Verification of HDL Models [Anglais] [Relié]

Janick Bergeron


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Première phrase
Verification is not a testbench, nor is it a series of testbenches. Lire la première page
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Concordance
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Couverture | Copyright | Table des matières | Extrait | Index | Quatrième de couverture
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Amazon.com: 3.8 étoiles sur 5  9 commentaires
7 internautes sur 7 ont trouvé ce commentaire utile 
3.0 étoiles sur 5 Some interesting parts, but mostly a collection of 'tricks'. 2 juin 2005
Par Amazon Customer - Publié sur Amazon.com
Format:Relié|Achat vérifié
This book covers many facets of the task of creating testbenches. However, it doesn't seem to follow a very well thought out plan, and there are holes in the coverage.

Most of the book is a 'tips and tricks' coverage of how to get each language to do what it wasn't designed to do. He walks through various situations and says that something is easy to do in Specman (shows a short code fragment), but then goes into long detail in how to get around VHDL's limitations and get the same result. I realize these are probably pretty cool tricks, but not at all the approach for me (a beginner to writing sizable testbenches). If he kept up the coverage of all 4 languages throughout, it might be useful, but the focus shifts from language to language at whim. You won't learn how to write a testbench as much as you will learn some pitfalls to avoid.

One more gripe before I get to the parts I liked. Each chapter ends with a summary. The summary lists the author's favorite tricks, not a summary of the whole chapter. I found these to be not at all helpful in either deciding whether to read the chapter, or as a review of what was covered.

I did like the explanations of:

-- The importance of verification (now I know why I was hired)

-- Overview of all the lingo (I can sound like I know what I'm talking about now, even if I don't)

-- Merits of the various types of coverage (code/functional/transition ...)

-- Aspect Oriented Programming (e) and why it is useful (cool stuff!)

-- Using coverage to drive a random bench

That is only about 10% of the book, however. That 10% was really pretty good.

I see one of the other reviewers complained about lack of downloadable sourcecode. It is available at [...] along with an extensive errata list (I'd recommend taking the hour or so and marking up your book before reading).

I still give the book 3 stars, since it is the only verification book I've found, and I did really like parts of it. I read the book front to back, and would not particularly recommend this to others. Pick the parts that interest you, and skip the rest.
8 internautes sur 9 ont trouvé ce commentaire utile 
3.0 étoiles sur 5 Great start but needs work 20 octobre 2001
Par Niel Slaughter - Publié sur Amazon.com
Format:Relié
It is great that we, as verification engineers, finally have a book focusing on streamlining and improving the verification process. This book covers all the basics for building a verification plan, implementing it, and maintaining it. It also includes a very large compliment of examples right alongside the concepts to improve understanding. However, it is unfortunate that the author is caught not following his own principles in each example. I feel that I would learn his principles better through repetition, where each example builds on the concepts already presented. He presents bus functional models in one chapter, then starts again at the top in the next. This makes it hard for me to see the big picture. One large example at the end could make it easier for me to see all his principles together in one testbench. Otherwise I'm stuck taking notes...
8 internautes sur 10 ont trouvé ce commentaire utile 
4.0 étoiles sur 5 Great content - can't wait for next edition 27 mai 2003
Par Not My Real Name - Publié sur Amazon.com
Format:Relié
I loved the book and it provided much information I needed - in a convoluted manner. I'm sure that Janick will improve upon this in the next edition and provide examples we all can use.
Thank you for the book and it's content - To my knowledge 15 people I know have purchased it upon my recommendation.
8 internautes sur 10 ont trouvé ce commentaire utile 
5.0 étoiles sur 5 The First of Its Kind 17 mai 2002
Par Edwin Aquino - Publié sur Amazon.com
Format:Relié
I have been working with VHDL and Verilog for years but this
is the first book that treats the subject of testbenches seriously and comprehensively in both language.
I collect books and this is one of the best written books in my shelf. Highly recommended
12 internautes sur 17 ont trouvé ce commentaire utile 
3.0 étoiles sur 5 Sunburst Design Book Review 17 octobre 2001
Par Clifford E. Cummings - Publié sur Amazon.com
Format:Relié
The book was great actually earning 3-1/2 out of 5 stars (the examples need to be debugged, tested and put online to merit 4 stars - I disagree with too many of the coding and methodology recommendations to award 5 stars). In my opinion, because the code examples are not full, because the code is not fully tested, and because not all examples are written in both Verilog and VHDL, the book is geared more to advanced users who can extrapolate the missing information and identify the mistakes in the code. The book will be best understood by experienced engineers who know both languages so that they can extract all of the relevant points. I disagree with a number of Janick's recommendations. A full review of this book is available on the sunburst-design web site.
This is the first technical book that I have read from cover-to-cover (minus a couple of the larger VHDL examples). I picked up a few techniques and tricks that I had not thought of before and that I intend to use. Although I may appear to be overly critical of Janick in my full review, I only do in-depth critiques of books that I deem worthy of recommending. Nice job, Janick!
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