Writing Testbenches: Functional Verification of Hdl Models (Anglais) Relié – janvier 2003
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Commentaires client les plus utiles sur Amazon.com
Most of the book is a 'tips and tricks' coverage of how to get each language to do what it wasn't designed to do. He walks through various situations and says that something is easy to do in Specman (shows a short code fragment), but then goes into long detail in how to get around VHDL's limitations and get the same result. I realize these are probably pretty cool tricks, but not at all the approach for me (a beginner to writing sizable testbenches). If he kept up the coverage of all 4 languages throughout, it might be useful, but the focus shifts from language to language at whim. You won't learn how to write a testbench as much as you will learn some pitfalls to avoid.
One more gripe before I get to the parts I liked. Each chapter ends with a summary. The summary lists the author's favorite tricks, not a summary of the whole chapter. I found these to be not at all helpful in either deciding whether to read the chapter, or as a review of what was covered.
I did like the explanations of:
-- The importance of verification (now I know why I was hired)
-- Overview of all the lingo (I can sound like I know what I'm talking about now, even if I don't)
-- Merits of the various types of coverage (code/functional/transition ...)
-- Aspect Oriented Programming (e) and why it is useful (cool stuff!)
-- Using coverage to drive a random bench
That is only about 10% of the book, however. That 10% was really pretty good.
I see one of the other reviewers complained about lack of downloadable sourcecode. It is available at [...] along with an extensive errata list (I'd recommend taking the hour or so and marking up your book before reading).
I still give the book 3 stars, since it is the only verification book I've found, and I did really like parts of it. I read the book front to back, and would not particularly recommend this to others. Pick the parts that interest you, and skip the rest.
Of the books purchased so far, this is book is genuinely unique and a worthwhile purchase. One of my mentor's advised that books on verification are rare, he thought there was one other, but I couldn't find it.
While I am still studying this book, I have found it to be the BEST I have purchased by far. It provides a unique insight into HDL design and verification. While it amazes many to read that so little work has been done in formalizing testing, a field consuming some 70 or more percent of design time, Janick provides an extremely valuable contribution.
The content covers both Verilog and VHDL coding so suits everyone and contains ample code in both languages to illustrate the points raised. It starts with a case study of a bridge that collapsed to demonstrate the need and continues in a logical and comprehensible manner.
The content builds in a way that a neophyte can easily understand, yet also would bore an experienced designer. Everyone in this field will learn useful skills
There are a lot of hackneyed superlatives one could use to describe this work. In restricting myself to one, I choose seminal.
The book has one minor drawback, my fourth print copy has a number of errors, in fact most of those from the second printing. Corrections are posted on the web site.
While I am reluctant to recommend books because it inflates expectations, I encourage every HDL designer and student to get this book and the corrections. It is a classic and will serve you very well for a long time!
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